Power Comparison Of Cmos And Full Adder Circuits

Authors

  • NEERAJ CHOUDHARY Research Scholar, Department of Electronics and communication, CBS Groups of Institutions
  • SHIPRA SHARMA Department of Electronics and communication, CBS Groups of Institutions

Keywords:

Low-power, CMOS, Full adder, Pass transistor logic, CMOS Transmission gate, Static Energy Recovery Full adder, Adder9A, Adder9B, channel length

Abstract

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and different types of full adder circuits are analyzed in terms of power and delay. A metric to evaluate full adder circuit performance is power delay product (PDP). The driving capability of full adder is very important, because, full adders are mostly used in cascade configuration, where output of one provides the input for others. If full adders lack driving capability then it requires additional buffer which consequently increases the power dissipation.

References

A. Chandrakasan, R. Brodersen, ―Low Power Design‖, Kluwer Academic Publishers, 1995.

A. M. Shams, and M. A. Bayoumi, ―A Novel High Performance CMOS 1-Bit Full Adder Cell‖, IEEE Transactions on Circuit and System, vol.47, NO. 5, May, 2000.

J. H. Kang and J. B. Kim, ―Design of a Low Power CVSL Full Adder Using Low-Swing Technique‖, ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia.

A. A. Khatibzadeh and K. Raahemifar, ―A Study and Comparison of Full Adder Cells based on the Standard Static CMOS Logic.‖, IEEE CCECE 2004 - CCGEI 2004, Niagara Falls, May 2004.

S. M. Kang and Y. Leblebici, ―CMOS Digital Integrated Circuits: Analysis and Design‖, Third Edition, Tata McGraw-Hill Edition 2003, pp 307-316.

A. Morgenshtein, A. Fish and A. Wagner, ―Gate-Diffusion Input(GDI): A Power-Efficient Method for Digital Combinational Circuits‖, IEEE Trans.

VLSI Syst., pp. 566-581, Oct. 2002.

I. Hassoune, D.Flandre, I. O’Connor and J. D. Legat, ―ULPFA: a new efficient design of a power aware full adder‖, IEEE Transactions on Circuits and Systems I-5438, 2008.

R. Zimmermann and W. Fichter, ―Low –power logic styles: CMOS versus pass-transistor logic,‖ IEEE J. Solid-State Circuits, Vol. 32, July 1997, pp.1079-90

N. Weste and K. Eshraghian, ―Principles of VLSI Design, A System Perspective‖, Reading, MA: Addison-Wesley, 1993.

N. Zhuang and H. Wu, ―New Design of the CMOS Full Adder‖, IEEE J. Solid-State Circuits, vol. 27,no. 5,pp. 840-844, May 1992

J. Wang, S. Fang, and W. Feng, ―New efficient designs for XOR and XNOR functions on the transistor level‖, IEEE J. Solid-State Circuits, vol. 29, no. 7, Jul. 1994, pp. 780–786.

R. Shalem, E. John, and L. K. John, ―A Novel Low Power Energy Recovery Full Adder Cell‖ in Proc. IEEE Great Lakes VLSI Symp., pp. 380–383, Feb. 1999.

Downloads

Published

31-12-2016

How to Cite

NEERAJ CHOUDHARY, & SHIPRA SHARMA. (2016). Power Comparison Of Cmos And Full Adder Circuits. International Journal for Research Publication and Seminar, 7(9). Retrieved from https://jrps.shodhsagar.com/index.php/j/article/view/1384

Issue

Vol. 7 No. 9 (2016): Oct - Dec 2016

Section

Original Research Article

License

Copyright (c) 2016 International Journal for Research Publication and Seminar

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

Re-users must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use. This license allows for redistribution, commercial and non-commercial, as long as the original work is properly credited.