ANALYSIS OF 16 BIT RISC PROCESSOR USING LOW POWER PIPELINING

Authors

  • Shweta S. Chimurkar M.Tech Student Department Of Electronics Engineering Priyadarshini College of Engineering Nagpur, India
  • Prof. P. J. Suryawanshi Assistant Professor Department Of Electronics Engineering Priyadarshini College of Engineering Nagpur, India

Keywords:

Pipelining, Xilinx, RISC, Low Power

Abstract

The aim of the paper is to design a 16-bit RISC processor. It is having four stages pipelining which is designed using VHDL. RISC processors have a unique feature called pipelining. Pipelining is used to make processor faster. In Pipelining instruction cycle is divided into parts so that more than one instruction can be operated in parallel. Number of instructions is designed for these processors. Multiplier is also designed using ADD instruction. Proposed instructions are simulated using Xilinx ISE 13.2. A 16-bit low power pipelined RISC processor is proposed by us in this project, the RISC processor consists of the block mainly ALU, program counter , ram, instruction memory ,2:1 mux. This project presents the design and implementation of a low power pipelined 16-bit RISC Processor. In this project, low power technique is proposed in front end process. Low power consumption helps to reduce the heat dissipation, lengthen battery life and increase device reliability.

References

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Published

30-06-2018

How to Cite

Shweta S. Chimurkar, & Prof. P. J. Suryawanshi. (2018). ANALYSIS OF 16 BIT RISC PROCESSOR USING LOW POWER PIPELINING. International Journal for Research Publication and Seminar, 9(2), 14–18. Retrieved from https://jrps.shodhsagar.com/index.php/j/article/view/1317

Issue

Vol. 9 No. 2 (2018): Apr - Jun 2018

Section

Original Research Article

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Copyright (c) 2018 International Journal for Research Publication and Seminar

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